firmware-nucleo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h (12582B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_pwr.h 4 * @author MCD Application Team 5 * @brief Header file of PWR LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F1xx_LL_PWR_H 21 #define __STM32F1xx_LL_PWR_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f1xx.h" 29 30 /** @addtogroup STM32F1xx_LL_Driver 31 * @{ 32 */ 33 34 #if defined(PWR) 35 36 /** @defgroup PWR_LL PWR 37 * @{ 38 */ 39 40 /* Private types -------------------------------------------------------------*/ 41 /* Private variables ---------------------------------------------------------*/ 42 /* Private constants ---------------------------------------------------------*/ 43 /* Private macros ------------------------------------------------------------*/ 44 /* Exported types ------------------------------------------------------------*/ 45 /* Exported constants --------------------------------------------------------*/ 46 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants 47 * @{ 48 */ 49 50 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines 51 * @brief Flags defines which can be used with LL_PWR_WriteReg function 52 * @{ 53 */ 54 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ 55 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ 56 /** 57 * @} 58 */ 59 60 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines 61 * @brief Flags defines which can be used with LL_PWR_ReadReg function 62 * @{ 63 */ 64 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ 65 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ 66 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ 67 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */ 68 /** 69 * @} 70 */ 71 72 73 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power 74 * @{ 75 */ 76 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ 77 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ 78 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ 79 /** 80 * @} 81 */ 82 83 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode 84 * @{ 85 */ 86 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ 87 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ 88 /** 89 * @} 90 */ 91 92 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level 93 * @{ 94 */ 95 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ 96 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ 97 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ 98 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ 99 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ 100 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ 101 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ 102 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ 103 /** 104 * @} 105 */ 106 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins 107 * @{ 108 */ 109 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */ 110 /** 111 * @} 112 */ 113 114 /** 115 * @} 116 */ 117 118 119 /* Exported macro ------------------------------------------------------------*/ 120 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros 121 * @{ 122 */ 123 124 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros 125 * @{ 126 */ 127 128 /** 129 * @brief Write a value in PWR register 130 * @param __REG__ Register to be written 131 * @param __VALUE__ Value to be written in the register 132 * @retval None 133 */ 134 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) 135 136 /** 137 * @brief Read a value in PWR register 138 * @param __REG__ Register to be read 139 * @retval Register value 140 */ 141 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) 142 /** 143 * @} 144 */ 145 146 /** 147 * @} 148 */ 149 150 /* Exported functions --------------------------------------------------------*/ 151 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions 152 * @{ 153 */ 154 155 /** @defgroup PWR_LL_EF_Configuration Configuration 156 * @{ 157 */ 158 159 /** 160 * @brief Enable access to the backup domain 161 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess 162 * @retval None 163 */ 164 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) 165 { 166 SET_BIT(PWR->CR, PWR_CR_DBP); 167 } 168 169 /** 170 * @brief Disable access to the backup domain 171 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess 172 * @retval None 173 */ 174 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) 175 { 176 CLEAR_BIT(PWR->CR, PWR_CR_DBP); 177 } 178 179 /** 180 * @brief Check if the backup domain is enabled 181 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess 182 * @retval State of bit (1 or 0). 183 */ 184 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) 185 { 186 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); 187 } 188 189 /** 190 * @brief Set voltage Regulator mode during deep sleep mode 191 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS 192 * @param RegulMode This parameter can be one of the following values: 193 * @arg @ref LL_PWR_REGU_DSMODE_MAIN 194 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER 195 * @retval None 196 */ 197 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) 198 { 199 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); 200 } 201 202 /** 203 * @brief Get voltage Regulator mode during deep sleep mode 204 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS 205 * @retval Returned value can be one of the following values: 206 * @arg @ref LL_PWR_REGU_DSMODE_MAIN 207 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER 208 */ 209 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) 210 { 211 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); 212 } 213 214 /** 215 * @brief Set Power Down mode when CPU enters deepsleep 216 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n 217 * @rmtoll CR LPDS LL_PWR_SetPowerMode 218 * @param PDMode This parameter can be one of the following values: 219 * @arg @ref LL_PWR_MODE_STOP_MAINREGU 220 * @arg @ref LL_PWR_MODE_STOP_LPREGU 221 * @arg @ref LL_PWR_MODE_STANDBY 222 * @retval None 223 */ 224 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) 225 { 226 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); 227 } 228 229 /** 230 * @brief Get Power Down mode when CPU enters deepsleep 231 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n 232 * @rmtoll CR LPDS LL_PWR_GetPowerMode 233 * @retval Returned value can be one of the following values: 234 * @arg @ref LL_PWR_MODE_STOP_MAINREGU 235 * @arg @ref LL_PWR_MODE_STOP_LPREGU 236 * @arg @ref LL_PWR_MODE_STANDBY 237 */ 238 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) 239 { 240 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); 241 } 242 243 /** 244 * @brief Configure the voltage threshold detected by the Power Voltage Detector 245 * @rmtoll CR PLS LL_PWR_SetPVDLevel 246 * @param PVDLevel This parameter can be one of the following values: 247 * @arg @ref LL_PWR_PVDLEVEL_0 248 * @arg @ref LL_PWR_PVDLEVEL_1 249 * @arg @ref LL_PWR_PVDLEVEL_2 250 * @arg @ref LL_PWR_PVDLEVEL_3 251 * @arg @ref LL_PWR_PVDLEVEL_4 252 * @arg @ref LL_PWR_PVDLEVEL_5 253 * @arg @ref LL_PWR_PVDLEVEL_6 254 * @arg @ref LL_PWR_PVDLEVEL_7 255 * @retval None 256 */ 257 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) 258 { 259 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); 260 } 261 262 /** 263 * @brief Get the voltage threshold detection 264 * @rmtoll CR PLS LL_PWR_GetPVDLevel 265 * @retval Returned value can be one of the following values: 266 * @arg @ref LL_PWR_PVDLEVEL_0 267 * @arg @ref LL_PWR_PVDLEVEL_1 268 * @arg @ref LL_PWR_PVDLEVEL_2 269 * @arg @ref LL_PWR_PVDLEVEL_3 270 * @arg @ref LL_PWR_PVDLEVEL_4 271 * @arg @ref LL_PWR_PVDLEVEL_5 272 * @arg @ref LL_PWR_PVDLEVEL_6 273 * @arg @ref LL_PWR_PVDLEVEL_7 274 */ 275 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) 276 { 277 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); 278 } 279 280 /** 281 * @brief Enable Power Voltage Detector 282 * @rmtoll CR PVDE LL_PWR_EnablePVD 283 * @retval None 284 */ 285 __STATIC_INLINE void LL_PWR_EnablePVD(void) 286 { 287 SET_BIT(PWR->CR, PWR_CR_PVDE); 288 } 289 290 /** 291 * @brief Disable Power Voltage Detector 292 * @rmtoll CR PVDE LL_PWR_DisablePVD 293 * @retval None 294 */ 295 __STATIC_INLINE void LL_PWR_DisablePVD(void) 296 { 297 CLEAR_BIT(PWR->CR, PWR_CR_PVDE); 298 } 299 300 /** 301 * @brief Check if Power Voltage Detector is enabled 302 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD 303 * @retval State of bit (1 or 0). 304 */ 305 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) 306 { 307 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); 308 } 309 310 /** 311 * @brief Enable the WakeUp PINx functionality 312 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin 313 * @param WakeUpPin This parameter can be one of the following values: 314 * @arg @ref LL_PWR_WAKEUP_PIN1 315 * @retval None 316 */ 317 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) 318 { 319 SET_BIT(PWR->CSR, WakeUpPin); 320 } 321 322 /** 323 * @brief Disable the WakeUp PINx functionality 324 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin 325 * @param WakeUpPin This parameter can be one of the following values: 326 * @arg @ref LL_PWR_WAKEUP_PIN1 327 * @retval None 328 */ 329 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) 330 { 331 CLEAR_BIT(PWR->CSR, WakeUpPin); 332 } 333 334 /** 335 * @brief Check if the WakeUp PINx functionality is enabled 336 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin 337 * @param WakeUpPin This parameter can be one of the following values: 338 * @arg @ref LL_PWR_WAKEUP_PIN1 339 * @retval State of bit (1 or 0). 340 */ 341 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) 342 { 343 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); 344 } 345 346 347 /** 348 * @} 349 */ 350 351 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management 352 * @{ 353 */ 354 355 /** 356 * @brief Get Wake-up Flag 357 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU 358 * @retval State of bit (1 or 0). 359 */ 360 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) 361 { 362 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); 363 } 364 365 /** 366 * @brief Get Standby Flag 367 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB 368 * @retval State of bit (1 or 0). 369 */ 370 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) 371 { 372 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); 373 } 374 375 /** 376 * @brief Indicate whether VDD voltage is below the selected PVD threshold 377 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO 378 * @retval State of bit (1 or 0). 379 */ 380 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) 381 { 382 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); 383 } 384 385 /** 386 * @brief Clear Standby Flag 387 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB 388 * @retval None 389 */ 390 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) 391 { 392 SET_BIT(PWR->CR, PWR_CR_CSBF); 393 } 394 395 /** 396 * @brief Clear Wake-up Flags 397 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU 398 * @retval None 399 */ 400 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) 401 { 402 SET_BIT(PWR->CR, PWR_CR_CWUF); 403 } 404 405 /** 406 * @} 407 */ 408 409 #if defined(USE_FULL_LL_DRIVER) 410 /** @defgroup PWR_LL_EF_Init De-initialization function 411 * @{ 412 */ 413 ErrorStatus LL_PWR_DeInit(void); 414 /** 415 * @} 416 */ 417 #endif /* USE_FULL_LL_DRIVER */ 418 419 /** 420 * @} 421 */ 422 423 /** 424 * @} 425 */ 426 427 #endif /* defined(PWR) */ 428 429 /** 430 * @} 431 */ 432 433 #ifdef __cplusplus 434 } 435 #endif 436 437 #endif /* __STM32F1xx_LL_PWR_H */