firmware-nucleo/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h (76231B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F1xx_LL_DMA_H 21 #define __STM32F1xx_LL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f1xx.h" 29 30 /** @addtogroup STM32F1xx_LL_Driver 31 * @{ 32 */ 33 34 #if defined (DMA1) || defined (DMA2) 35 36 /** @defgroup DMA_LL DMA 37 * @{ 38 */ 39 40 /* Private types -------------------------------------------------------------*/ 41 /* Private variables ---------------------------------------------------------*/ 42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 43 * @{ 44 */ 45 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ 46 static const uint8_t CHANNEL_OFFSET_TAB[] = 47 { 48 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 49 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 50 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 51 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 52 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 53 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 54 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) 55 }; 56 /** 57 * @} 58 */ 59 /* Private constants ---------------------------------------------------------*/ 60 /* Private macros ------------------------------------------------------------*/ 61 #if defined(USE_FULL_LL_DRIVER) 62 /** @defgroup DMA_LL_Private_Macros DMA Private Macros 63 * @{ 64 */ 65 /** 66 * @} 67 */ 68 #endif /*USE_FULL_LL_DRIVER*/ 69 70 /* Exported types ------------------------------------------------------------*/ 71 #if defined(USE_FULL_LL_DRIVER) 72 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 73 * @{ 74 */ 75 typedef struct 76 { 77 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 78 or as Source base address in case of memory to memory transfer direction. 79 80 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 81 82 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 83 or as Destination base address in case of memory to memory transfer direction. 84 85 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 86 87 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 88 from memory to memory or from peripheral to memory. 89 This parameter can be a value of @ref DMA_LL_EC_DIRECTION 90 91 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ 92 93 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 94 This parameter can be a value of @ref DMA_LL_EC_MODE 95 @note: The circular buffer mode cannot be used if the memory to memory 96 data transfer direction is configured on the selected Channel 97 98 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ 99 100 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 101 is incremented or not. 102 This parameter can be a value of @ref DMA_LL_EC_PERIPH 103 104 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ 105 106 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 107 is incremented or not. 108 This parameter can be a value of @ref DMA_LL_EC_MEMORY 109 110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ 111 112 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 113 in case of memory to memory transfer direction. 114 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 115 116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ 117 118 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 119 in case of memory to memory transfer direction. 120 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 121 122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ 123 124 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 125 The data unit is equal to the source buffer configuration set in PeripheralSize 126 or MemorySize parameters depending in the transfer direction. 127 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 128 129 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ 130 131 uint32_t Priority; /*!< Specifies the channel priority level. 132 This parameter can be a value of @ref DMA_LL_EC_PRIORITY 133 134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ 135 136 } LL_DMA_InitTypeDef; 137 /** 138 * @} 139 */ 140 #endif /*USE_FULL_LL_DRIVER*/ 141 142 /* Exported constants --------------------------------------------------------*/ 143 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 144 * @{ 145 */ 146 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines 147 * @brief Flags defines which can be used with LL_DMA_WriteReg function 148 * @{ 149 */ 150 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ 151 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ 152 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ 153 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ 154 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ 155 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ 156 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ 157 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ 158 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ 159 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ 160 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ 161 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ 162 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ 163 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ 164 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ 165 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ 166 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ 167 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ 168 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ 169 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ 170 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ 171 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ 172 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ 173 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ 174 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ 175 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ 176 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ 177 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ 178 /** 179 * @} 180 */ 181 182 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines 183 * @brief Flags defines which can be used with LL_DMA_ReadReg function 184 * @{ 185 */ 186 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ 187 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 188 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 189 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 190 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ 191 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 192 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 193 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 194 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ 195 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 196 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 197 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 198 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ 199 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 200 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 201 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 202 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ 203 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 204 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 205 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 206 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ 207 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 208 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 209 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 210 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ 211 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 212 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 213 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup DMA_LL_EC_IT IT Defines 219 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions 220 * @{ 221 */ 222 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ 223 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ 224 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 230 * @{ 231 */ 232 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ 233 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ 234 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ 235 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ 236 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ 237 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ 238 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ 239 #if defined(USE_FULL_LL_DRIVER) 240 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ 241 #endif /*USE_FULL_LL_DRIVER*/ 242 /** 243 * @} 244 */ 245 246 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction 247 * @{ 248 */ 249 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 250 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 251 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 252 /** 253 * @} 254 */ 255 256 /** @defgroup DMA_LL_EC_MODE Transfer mode 257 * @{ 258 */ 259 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 260 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ 261 /** 262 * @} 263 */ 264 265 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode 266 * @{ 267 */ 268 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 269 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode 275 * @{ 276 */ 277 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ 278 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 279 /** 280 * @} 281 */ 282 283 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment 284 * @{ 285 */ 286 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 287 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 288 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 289 /** 290 * @} 291 */ 292 293 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment 294 * @{ 295 */ 296 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 297 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 298 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 299 /** 300 * @} 301 */ 302 303 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level 304 * @{ 305 */ 306 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 307 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 308 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 309 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ 310 /** 311 * @} 312 */ 313 314 /** 315 * @} 316 */ 317 318 /* Exported macro ------------------------------------------------------------*/ 319 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 320 * @{ 321 */ 322 323 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 324 * @{ 325 */ 326 /** 327 * @brief Write a value in DMA register 328 * @param __INSTANCE__ DMA Instance 329 * @param __REG__ Register to be written 330 * @param __VALUE__ Value to be written in the register 331 * @retval None 332 */ 333 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 334 335 /** 336 * @brief Read a value in DMA register 337 * @param __INSTANCE__ DMA Instance 338 * @param __REG__ Register to be read 339 * @retval Register value 340 */ 341 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 342 /** 343 * @} 344 */ 345 346 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely 347 * @{ 348 */ 349 350 /** 351 * @brief Convert DMAx_Channely into DMAx 352 * @param __CHANNEL_INSTANCE__ DMAx_Channely 353 * @retval DMAx 354 */ 355 #if defined(DMA2) 356 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ 357 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) 358 #else 359 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) 360 #endif 361 362 /** 363 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y 364 * @param __CHANNEL_INSTANCE__ DMAx_Channely 365 * @retval LL_DMA_CHANNEL_y 366 */ 367 #if defined (DMA2) 368 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 369 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 370 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ 371 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 372 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ 373 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 374 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ 375 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ 377 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 378 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ 379 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 380 LL_DMA_CHANNEL_7) 381 #else 382 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 383 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 384 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 385 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 386 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 387 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 388 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 389 LL_DMA_CHANNEL_7) 390 #endif 391 392 /** 393 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely 394 * @param __DMA_INSTANCE__ DMAx 395 * @param __CHANNEL__ LL_DMA_CHANNEL_y 396 * @retval DMAx_Channely 397 */ 398 #if defined (DMA2) 399 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 400 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 401 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ 402 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 403 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ 404 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 405 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ 406 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 407 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ 408 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 409 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ 410 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 411 DMA1_Channel7) 412 #else 413 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 414 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 415 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 416 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 417 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 418 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 419 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 420 DMA1_Channel7) 421 #endif 422 423 /** 424 * @} 425 */ 426 427 /** 428 * @} 429 */ 430 431 /* Exported functions --------------------------------------------------------*/ 432 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 433 * @{ 434 */ 435 436 /** @defgroup DMA_LL_EF_Configuration Configuration 437 * @{ 438 */ 439 /** 440 * @brief Enable DMA channel. 441 * @rmtoll CCR EN LL_DMA_EnableChannel 442 * @param DMAx DMAx Instance 443 * @param Channel This parameter can be one of the following values: 444 * @arg @ref LL_DMA_CHANNEL_1 445 * @arg @ref LL_DMA_CHANNEL_2 446 * @arg @ref LL_DMA_CHANNEL_3 447 * @arg @ref LL_DMA_CHANNEL_4 448 * @arg @ref LL_DMA_CHANNEL_5 449 * @arg @ref LL_DMA_CHANNEL_6 450 * @arg @ref LL_DMA_CHANNEL_7 451 * @retval None 452 */ 453 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 454 { 455 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); 456 } 457 458 /** 459 * @brief Disable DMA channel. 460 * @rmtoll CCR EN LL_DMA_DisableChannel 461 * @param DMAx DMAx Instance 462 * @param Channel This parameter can be one of the following values: 463 * @arg @ref LL_DMA_CHANNEL_1 464 * @arg @ref LL_DMA_CHANNEL_2 465 * @arg @ref LL_DMA_CHANNEL_3 466 * @arg @ref LL_DMA_CHANNEL_4 467 * @arg @ref LL_DMA_CHANNEL_5 468 * @arg @ref LL_DMA_CHANNEL_6 469 * @arg @ref LL_DMA_CHANNEL_7 470 * @retval None 471 */ 472 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 473 { 474 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); 475 } 476 477 /** 478 * @brief Check if DMA channel is enabled or disabled. 479 * @rmtoll CCR EN LL_DMA_IsEnabledChannel 480 * @param DMAx DMAx Instance 481 * @param Channel This parameter can be one of the following values: 482 * @arg @ref LL_DMA_CHANNEL_1 483 * @arg @ref LL_DMA_CHANNEL_2 484 * @arg @ref LL_DMA_CHANNEL_3 485 * @arg @ref LL_DMA_CHANNEL_4 486 * @arg @ref LL_DMA_CHANNEL_5 487 * @arg @ref LL_DMA_CHANNEL_6 488 * @arg @ref LL_DMA_CHANNEL_7 489 * @retval State of bit (1 or 0). 490 */ 491 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) 492 { 493 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 494 DMA_CCR_EN) == (DMA_CCR_EN)); 495 } 496 497 /** 498 * @brief Configure all parameters link to DMA transfer. 499 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n 500 * CCR MEM2MEM LL_DMA_ConfigTransfer\n 501 * CCR CIRC LL_DMA_ConfigTransfer\n 502 * CCR PINC LL_DMA_ConfigTransfer\n 503 * CCR MINC LL_DMA_ConfigTransfer\n 504 * CCR PSIZE LL_DMA_ConfigTransfer\n 505 * CCR MSIZE LL_DMA_ConfigTransfer\n 506 * CCR PL LL_DMA_ConfigTransfer 507 * @param DMAx DMAx Instance 508 * @param Channel This parameter can be one of the following values: 509 * @arg @ref LL_DMA_CHANNEL_1 510 * @arg @ref LL_DMA_CHANNEL_2 511 * @arg @ref LL_DMA_CHANNEL_3 512 * @arg @ref LL_DMA_CHANNEL_4 513 * @arg @ref LL_DMA_CHANNEL_5 514 * @arg @ref LL_DMA_CHANNEL_6 515 * @arg @ref LL_DMA_CHANNEL_7 516 * @param Configuration This parameter must be a combination of all the following values: 517 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 518 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR 519 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 520 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 521 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 522 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 523 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 524 * @retval None 525 */ 526 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) 527 { 528 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 529 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, 530 Configuration); 531 } 532 533 /** 534 * @brief Set Data transfer direction (read from peripheral or from memory). 535 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n 536 * CCR MEM2MEM LL_DMA_SetDataTransferDirection 537 * @param DMAx DMAx Instance 538 * @param Channel This parameter can be one of the following values: 539 * @arg @ref LL_DMA_CHANNEL_1 540 * @arg @ref LL_DMA_CHANNEL_2 541 * @arg @ref LL_DMA_CHANNEL_3 542 * @arg @ref LL_DMA_CHANNEL_4 543 * @arg @ref LL_DMA_CHANNEL_5 544 * @arg @ref LL_DMA_CHANNEL_6 545 * @arg @ref LL_DMA_CHANNEL_7 546 * @param Direction This parameter can be one of the following values: 547 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 548 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 549 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 550 * @retval None 551 */ 552 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) 553 { 554 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 555 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); 556 } 557 558 /** 559 * @brief Get Data transfer direction (read from peripheral or from memory). 560 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n 561 * CCR MEM2MEM LL_DMA_GetDataTransferDirection 562 * @param DMAx DMAx Instance 563 * @param Channel This parameter can be one of the following values: 564 * @arg @ref LL_DMA_CHANNEL_1 565 * @arg @ref LL_DMA_CHANNEL_2 566 * @arg @ref LL_DMA_CHANNEL_3 567 * @arg @ref LL_DMA_CHANNEL_4 568 * @arg @ref LL_DMA_CHANNEL_5 569 * @arg @ref LL_DMA_CHANNEL_6 570 * @arg @ref LL_DMA_CHANNEL_7 571 * @retval Returned value can be one of the following values: 572 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 573 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 574 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 575 */ 576 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) 577 { 578 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 579 DMA_CCR_DIR | DMA_CCR_MEM2MEM)); 580 } 581 582 /** 583 * @brief Set DMA mode circular or normal. 584 * @note The circular buffer mode cannot be used if the memory-to-memory 585 * data transfer is configured on the selected Channel. 586 * @rmtoll CCR CIRC LL_DMA_SetMode 587 * @param DMAx DMAx Instance 588 * @param Channel This parameter can be one of the following values: 589 * @arg @ref LL_DMA_CHANNEL_1 590 * @arg @ref LL_DMA_CHANNEL_2 591 * @arg @ref LL_DMA_CHANNEL_3 592 * @arg @ref LL_DMA_CHANNEL_4 593 * @arg @ref LL_DMA_CHANNEL_5 594 * @arg @ref LL_DMA_CHANNEL_6 595 * @arg @ref LL_DMA_CHANNEL_7 596 * @param Mode This parameter can be one of the following values: 597 * @arg @ref LL_DMA_MODE_NORMAL 598 * @arg @ref LL_DMA_MODE_CIRCULAR 599 * @retval None 600 */ 601 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) 602 { 603 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, 604 Mode); 605 } 606 607 /** 608 * @brief Get DMA mode circular or normal. 609 * @rmtoll CCR CIRC LL_DMA_GetMode 610 * @param DMAx DMAx Instance 611 * @param Channel This parameter can be one of the following values: 612 * @arg @ref LL_DMA_CHANNEL_1 613 * @arg @ref LL_DMA_CHANNEL_2 614 * @arg @ref LL_DMA_CHANNEL_3 615 * @arg @ref LL_DMA_CHANNEL_4 616 * @arg @ref LL_DMA_CHANNEL_5 617 * @arg @ref LL_DMA_CHANNEL_6 618 * @arg @ref LL_DMA_CHANNEL_7 619 * @retval Returned value can be one of the following values: 620 * @arg @ref LL_DMA_MODE_NORMAL 621 * @arg @ref LL_DMA_MODE_CIRCULAR 622 */ 623 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) 624 { 625 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 626 DMA_CCR_CIRC)); 627 } 628 629 /** 630 * @brief Set Peripheral increment mode. 631 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode 632 * @param DMAx DMAx Instance 633 * @param Channel This parameter can be one of the following values: 634 * @arg @ref LL_DMA_CHANNEL_1 635 * @arg @ref LL_DMA_CHANNEL_2 636 * @arg @ref LL_DMA_CHANNEL_3 637 * @arg @ref LL_DMA_CHANNEL_4 638 * @arg @ref LL_DMA_CHANNEL_5 639 * @arg @ref LL_DMA_CHANNEL_6 640 * @arg @ref LL_DMA_CHANNEL_7 641 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: 642 * @arg @ref LL_DMA_PERIPH_INCREMENT 643 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 644 * @retval None 645 */ 646 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) 647 { 648 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, 649 PeriphOrM2MSrcIncMode); 650 } 651 652 /** 653 * @brief Get Peripheral increment mode. 654 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode 655 * @param DMAx DMAx Instance 656 * @param Channel This parameter can be one of the following values: 657 * @arg @ref LL_DMA_CHANNEL_1 658 * @arg @ref LL_DMA_CHANNEL_2 659 * @arg @ref LL_DMA_CHANNEL_3 660 * @arg @ref LL_DMA_CHANNEL_4 661 * @arg @ref LL_DMA_CHANNEL_5 662 * @arg @ref LL_DMA_CHANNEL_6 663 * @arg @ref LL_DMA_CHANNEL_7 664 * @retval Returned value can be one of the following values: 665 * @arg @ref LL_DMA_PERIPH_INCREMENT 666 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 667 */ 668 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) 669 { 670 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 671 DMA_CCR_PINC)); 672 } 673 674 /** 675 * @brief Set Memory increment mode. 676 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode 677 * @param DMAx DMAx Instance 678 * @param Channel This parameter can be one of the following values: 679 * @arg @ref LL_DMA_CHANNEL_1 680 * @arg @ref LL_DMA_CHANNEL_2 681 * @arg @ref LL_DMA_CHANNEL_3 682 * @arg @ref LL_DMA_CHANNEL_4 683 * @arg @ref LL_DMA_CHANNEL_5 684 * @arg @ref LL_DMA_CHANNEL_6 685 * @arg @ref LL_DMA_CHANNEL_7 686 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: 687 * @arg @ref LL_DMA_MEMORY_INCREMENT 688 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 689 * @retval None 690 */ 691 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) 692 { 693 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, 694 MemoryOrM2MDstIncMode); 695 } 696 697 /** 698 * @brief Get Memory increment mode. 699 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode 700 * @param DMAx DMAx Instance 701 * @param Channel This parameter can be one of the following values: 702 * @arg @ref LL_DMA_CHANNEL_1 703 * @arg @ref LL_DMA_CHANNEL_2 704 * @arg @ref LL_DMA_CHANNEL_3 705 * @arg @ref LL_DMA_CHANNEL_4 706 * @arg @ref LL_DMA_CHANNEL_5 707 * @arg @ref LL_DMA_CHANNEL_6 708 * @arg @ref LL_DMA_CHANNEL_7 709 * @retval Returned value can be one of the following values: 710 * @arg @ref LL_DMA_MEMORY_INCREMENT 711 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 712 */ 713 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) 714 { 715 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 716 DMA_CCR_MINC)); 717 } 718 719 /** 720 * @brief Set Peripheral size. 721 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize 722 * @param DMAx DMAx Instance 723 * @param Channel This parameter can be one of the following values: 724 * @arg @ref LL_DMA_CHANNEL_1 725 * @arg @ref LL_DMA_CHANNEL_2 726 * @arg @ref LL_DMA_CHANNEL_3 727 * @arg @ref LL_DMA_CHANNEL_4 728 * @arg @ref LL_DMA_CHANNEL_5 729 * @arg @ref LL_DMA_CHANNEL_6 730 * @arg @ref LL_DMA_CHANNEL_7 731 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: 732 * @arg @ref LL_DMA_PDATAALIGN_BYTE 733 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 734 * @arg @ref LL_DMA_PDATAALIGN_WORD 735 * @retval None 736 */ 737 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) 738 { 739 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, 740 PeriphOrM2MSrcDataSize); 741 } 742 743 /** 744 * @brief Get Peripheral size. 745 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize 746 * @param DMAx DMAx Instance 747 * @param Channel This parameter can be one of the following values: 748 * @arg @ref LL_DMA_CHANNEL_1 749 * @arg @ref LL_DMA_CHANNEL_2 750 * @arg @ref LL_DMA_CHANNEL_3 751 * @arg @ref LL_DMA_CHANNEL_4 752 * @arg @ref LL_DMA_CHANNEL_5 753 * @arg @ref LL_DMA_CHANNEL_6 754 * @arg @ref LL_DMA_CHANNEL_7 755 * @retval Returned value can be one of the following values: 756 * @arg @ref LL_DMA_PDATAALIGN_BYTE 757 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 758 * @arg @ref LL_DMA_PDATAALIGN_WORD 759 */ 760 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) 761 { 762 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 763 DMA_CCR_PSIZE)); 764 } 765 766 /** 767 * @brief Set Memory size. 768 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize 769 * @param DMAx DMAx Instance 770 * @param Channel This parameter can be one of the following values: 771 * @arg @ref LL_DMA_CHANNEL_1 772 * @arg @ref LL_DMA_CHANNEL_2 773 * @arg @ref LL_DMA_CHANNEL_3 774 * @arg @ref LL_DMA_CHANNEL_4 775 * @arg @ref LL_DMA_CHANNEL_5 776 * @arg @ref LL_DMA_CHANNEL_6 777 * @arg @ref LL_DMA_CHANNEL_7 778 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: 779 * @arg @ref LL_DMA_MDATAALIGN_BYTE 780 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 781 * @arg @ref LL_DMA_MDATAALIGN_WORD 782 * @retval None 783 */ 784 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) 785 { 786 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, 787 MemoryOrM2MDstDataSize); 788 } 789 790 /** 791 * @brief Get Memory size. 792 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize 793 * @param DMAx DMAx Instance 794 * @param Channel This parameter can be one of the following values: 795 * @arg @ref LL_DMA_CHANNEL_1 796 * @arg @ref LL_DMA_CHANNEL_2 797 * @arg @ref LL_DMA_CHANNEL_3 798 * @arg @ref LL_DMA_CHANNEL_4 799 * @arg @ref LL_DMA_CHANNEL_5 800 * @arg @ref LL_DMA_CHANNEL_6 801 * @arg @ref LL_DMA_CHANNEL_7 802 * @retval Returned value can be one of the following values: 803 * @arg @ref LL_DMA_MDATAALIGN_BYTE 804 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 805 * @arg @ref LL_DMA_MDATAALIGN_WORD 806 */ 807 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) 808 { 809 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 810 DMA_CCR_MSIZE)); 811 } 812 813 /** 814 * @brief Set Channel priority level. 815 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel 816 * @param DMAx DMAx Instance 817 * @param Channel This parameter can be one of the following values: 818 * @arg @ref LL_DMA_CHANNEL_1 819 * @arg @ref LL_DMA_CHANNEL_2 820 * @arg @ref LL_DMA_CHANNEL_3 821 * @arg @ref LL_DMA_CHANNEL_4 822 * @arg @ref LL_DMA_CHANNEL_5 823 * @arg @ref LL_DMA_CHANNEL_6 824 * @arg @ref LL_DMA_CHANNEL_7 825 * @param Priority This parameter can be one of the following values: 826 * @arg @ref LL_DMA_PRIORITY_LOW 827 * @arg @ref LL_DMA_PRIORITY_MEDIUM 828 * @arg @ref LL_DMA_PRIORITY_HIGH 829 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 830 * @retval None 831 */ 832 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) 833 { 834 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, 835 Priority); 836 } 837 838 /** 839 * @brief Get Channel priority level. 840 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel 841 * @param DMAx DMAx Instance 842 * @param Channel This parameter can be one of the following values: 843 * @arg @ref LL_DMA_CHANNEL_1 844 * @arg @ref LL_DMA_CHANNEL_2 845 * @arg @ref LL_DMA_CHANNEL_3 846 * @arg @ref LL_DMA_CHANNEL_4 847 * @arg @ref LL_DMA_CHANNEL_5 848 * @arg @ref LL_DMA_CHANNEL_6 849 * @arg @ref LL_DMA_CHANNEL_7 850 * @retval Returned value can be one of the following values: 851 * @arg @ref LL_DMA_PRIORITY_LOW 852 * @arg @ref LL_DMA_PRIORITY_MEDIUM 853 * @arg @ref LL_DMA_PRIORITY_HIGH 854 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 855 */ 856 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) 857 { 858 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 859 DMA_CCR_PL)); 860 } 861 862 /** 863 * @brief Set Number of data to transfer. 864 * @note This action has no effect if 865 * channel is enabled. 866 * @rmtoll CNDTR NDT LL_DMA_SetDataLength 867 * @param DMAx DMAx Instance 868 * @param Channel This parameter can be one of the following values: 869 * @arg @ref LL_DMA_CHANNEL_1 870 * @arg @ref LL_DMA_CHANNEL_2 871 * @arg @ref LL_DMA_CHANNEL_3 872 * @arg @ref LL_DMA_CHANNEL_4 873 * @arg @ref LL_DMA_CHANNEL_5 874 * @arg @ref LL_DMA_CHANNEL_6 875 * @arg @ref LL_DMA_CHANNEL_7 876 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF 877 * @retval None 878 */ 879 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) 880 { 881 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, 882 DMA_CNDTR_NDT, NbData); 883 } 884 885 /** 886 * @brief Get Number of data to transfer. 887 * @note Once the channel is enabled, the return value indicate the 888 * remaining bytes to be transmitted. 889 * @rmtoll CNDTR NDT LL_DMA_GetDataLength 890 * @param DMAx DMAx Instance 891 * @param Channel This parameter can be one of the following values: 892 * @arg @ref LL_DMA_CHANNEL_1 893 * @arg @ref LL_DMA_CHANNEL_2 894 * @arg @ref LL_DMA_CHANNEL_3 895 * @arg @ref LL_DMA_CHANNEL_4 896 * @arg @ref LL_DMA_CHANNEL_5 897 * @arg @ref LL_DMA_CHANNEL_6 898 * @arg @ref LL_DMA_CHANNEL_7 899 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 900 */ 901 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) 902 { 903 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, 904 DMA_CNDTR_NDT)); 905 } 906 907 /** 908 * @brief Configure the Source and Destination addresses. 909 * @note This API must not be called when the DMA channel is enabled. 910 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). 911 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n 912 * CMAR MA LL_DMA_ConfigAddresses 913 * @param DMAx DMAx Instance 914 * @param Channel This parameter can be one of the following values: 915 * @arg @ref LL_DMA_CHANNEL_1 916 * @arg @ref LL_DMA_CHANNEL_2 917 * @arg @ref LL_DMA_CHANNEL_3 918 * @arg @ref LL_DMA_CHANNEL_4 919 * @arg @ref LL_DMA_CHANNEL_5 920 * @arg @ref LL_DMA_CHANNEL_6 921 * @arg @ref LL_DMA_CHANNEL_7 922 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 923 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 924 * @param Direction This parameter can be one of the following values: 925 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 926 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 927 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 928 * @retval None 929 */ 930 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, 931 uint32_t DstAddress, uint32_t Direction) 932 { 933 /* Direction Memory to Periph */ 934 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 935 { 936 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); 937 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); 938 } 939 /* Direction Periph to Memory and Memory to Memory */ 940 else 941 { 942 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); 943 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); 944 } 945 } 946 947 /** 948 * @brief Set the Memory address. 949 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 950 * @note This API must not be called when the DMA channel is enabled. 951 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress 952 * @param DMAx DMAx Instance 953 * @param Channel This parameter can be one of the following values: 954 * @arg @ref LL_DMA_CHANNEL_1 955 * @arg @ref LL_DMA_CHANNEL_2 956 * @arg @ref LL_DMA_CHANNEL_3 957 * @arg @ref LL_DMA_CHANNEL_4 958 * @arg @ref LL_DMA_CHANNEL_5 959 * @arg @ref LL_DMA_CHANNEL_6 960 * @arg @ref LL_DMA_CHANNEL_7 961 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 962 * @retval None 963 */ 964 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 965 { 966 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); 967 } 968 969 /** 970 * @brief Set the Peripheral address. 971 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 972 * @note This API must not be called when the DMA channel is enabled. 973 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress 974 * @param DMAx DMAx Instance 975 * @param Channel This parameter can be one of the following values: 976 * @arg @ref LL_DMA_CHANNEL_1 977 * @arg @ref LL_DMA_CHANNEL_2 978 * @arg @ref LL_DMA_CHANNEL_3 979 * @arg @ref LL_DMA_CHANNEL_4 980 * @arg @ref LL_DMA_CHANNEL_5 981 * @arg @ref LL_DMA_CHANNEL_6 982 * @arg @ref LL_DMA_CHANNEL_7 983 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 984 * @retval None 985 */ 986 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) 987 { 988 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); 989 } 990 991 /** 992 * @brief Get Memory address. 993 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 994 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress 995 * @param DMAx DMAx Instance 996 * @param Channel This parameter can be one of the following values: 997 * @arg @ref LL_DMA_CHANNEL_1 998 * @arg @ref LL_DMA_CHANNEL_2 999 * @arg @ref LL_DMA_CHANNEL_3 1000 * @arg @ref LL_DMA_CHANNEL_4 1001 * @arg @ref LL_DMA_CHANNEL_5 1002 * @arg @ref LL_DMA_CHANNEL_6 1003 * @arg @ref LL_DMA_CHANNEL_7 1004 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1005 */ 1006 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) 1007 { 1008 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); 1009 } 1010 1011 /** 1012 * @brief Get Peripheral address. 1013 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1014 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress 1015 * @param DMAx DMAx Instance 1016 * @param Channel This parameter can be one of the following values: 1017 * @arg @ref LL_DMA_CHANNEL_1 1018 * @arg @ref LL_DMA_CHANNEL_2 1019 * @arg @ref LL_DMA_CHANNEL_3 1020 * @arg @ref LL_DMA_CHANNEL_4 1021 * @arg @ref LL_DMA_CHANNEL_5 1022 * @arg @ref LL_DMA_CHANNEL_6 1023 * @arg @ref LL_DMA_CHANNEL_7 1024 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1025 */ 1026 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) 1027 { 1028 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); 1029 } 1030 1031 /** 1032 * @brief Set the Memory to Memory Source address. 1033 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1034 * @note This API must not be called when the DMA channel is enabled. 1035 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress 1036 * @param DMAx DMAx Instance 1037 * @param Channel This parameter can be one of the following values: 1038 * @arg @ref LL_DMA_CHANNEL_1 1039 * @arg @ref LL_DMA_CHANNEL_2 1040 * @arg @ref LL_DMA_CHANNEL_3 1041 * @arg @ref LL_DMA_CHANNEL_4 1042 * @arg @ref LL_DMA_CHANNEL_5 1043 * @arg @ref LL_DMA_CHANNEL_6 1044 * @arg @ref LL_DMA_CHANNEL_7 1045 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1046 * @retval None 1047 */ 1048 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 1049 { 1050 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); 1051 } 1052 1053 /** 1054 * @brief Set the Memory to Memory Destination address. 1055 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1056 * @note This API must not be called when the DMA channel is enabled. 1057 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress 1058 * @param DMAx DMAx Instance 1059 * @param Channel This parameter can be one of the following values: 1060 * @arg @ref LL_DMA_CHANNEL_1 1061 * @arg @ref LL_DMA_CHANNEL_2 1062 * @arg @ref LL_DMA_CHANNEL_3 1063 * @arg @ref LL_DMA_CHANNEL_4 1064 * @arg @ref LL_DMA_CHANNEL_5 1065 * @arg @ref LL_DMA_CHANNEL_6 1066 * @arg @ref LL_DMA_CHANNEL_7 1067 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1068 * @retval None 1069 */ 1070 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 1071 { 1072 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); 1073 } 1074 1075 /** 1076 * @brief Get the Memory to Memory Source address. 1077 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1078 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress 1079 * @param DMAx DMAx Instance 1080 * @param Channel This parameter can be one of the following values: 1081 * @arg @ref LL_DMA_CHANNEL_1 1082 * @arg @ref LL_DMA_CHANNEL_2 1083 * @arg @ref LL_DMA_CHANNEL_3 1084 * @arg @ref LL_DMA_CHANNEL_4 1085 * @arg @ref LL_DMA_CHANNEL_5 1086 * @arg @ref LL_DMA_CHANNEL_6 1087 * @arg @ref LL_DMA_CHANNEL_7 1088 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1089 */ 1090 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) 1091 { 1092 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); 1093 } 1094 1095 /** 1096 * @brief Get the Memory to Memory Destination address. 1097 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1098 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress 1099 * @param DMAx DMAx Instance 1100 * @param Channel This parameter can be one of the following values: 1101 * @arg @ref LL_DMA_CHANNEL_1 1102 * @arg @ref LL_DMA_CHANNEL_2 1103 * @arg @ref LL_DMA_CHANNEL_3 1104 * @arg @ref LL_DMA_CHANNEL_4 1105 * @arg @ref LL_DMA_CHANNEL_5 1106 * @arg @ref LL_DMA_CHANNEL_6 1107 * @arg @ref LL_DMA_CHANNEL_7 1108 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1109 */ 1110 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) 1111 { 1112 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); 1113 } 1114 1115 /** 1116 * @} 1117 */ 1118 1119 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 1120 * @{ 1121 */ 1122 1123 /** 1124 * @brief Get Channel 1 global interrupt flag. 1125 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 1126 * @param DMAx DMAx Instance 1127 * @retval State of bit (1 or 0). 1128 */ 1129 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) 1130 { 1131 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); 1132 } 1133 1134 /** 1135 * @brief Get Channel 2 global interrupt flag. 1136 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 1137 * @param DMAx DMAx Instance 1138 * @retval State of bit (1 or 0). 1139 */ 1140 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) 1141 { 1142 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); 1143 } 1144 1145 /** 1146 * @brief Get Channel 3 global interrupt flag. 1147 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 1148 * @param DMAx DMAx Instance 1149 * @retval State of bit (1 or 0). 1150 */ 1151 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) 1152 { 1153 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); 1154 } 1155 1156 /** 1157 * @brief Get Channel 4 global interrupt flag. 1158 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 1159 * @param DMAx DMAx Instance 1160 * @retval State of bit (1 or 0). 1161 */ 1162 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) 1163 { 1164 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); 1165 } 1166 1167 /** 1168 * @brief Get Channel 5 global interrupt flag. 1169 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 1170 * @param DMAx DMAx Instance 1171 * @retval State of bit (1 or 0). 1172 */ 1173 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) 1174 { 1175 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); 1176 } 1177 1178 /** 1179 * @brief Get Channel 6 global interrupt flag. 1180 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 1181 * @param DMAx DMAx Instance 1182 * @retval State of bit (1 or 0). 1183 */ 1184 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) 1185 { 1186 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); 1187 } 1188 1189 /** 1190 * @brief Get Channel 7 global interrupt flag. 1191 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 1192 * @param DMAx DMAx Instance 1193 * @retval State of bit (1 or 0). 1194 */ 1195 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) 1196 { 1197 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); 1198 } 1199 1200 /** 1201 * @brief Get Channel 1 transfer complete flag. 1202 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 1203 * @param DMAx DMAx Instance 1204 * @retval State of bit (1 or 0). 1205 */ 1206 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 1207 { 1208 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); 1209 } 1210 1211 /** 1212 * @brief Get Channel 2 transfer complete flag. 1213 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 1214 * @param DMAx DMAx Instance 1215 * @retval State of bit (1 or 0). 1216 */ 1217 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 1218 { 1219 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); 1220 } 1221 1222 /** 1223 * @brief Get Channel 3 transfer complete flag. 1224 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 1225 * @param DMAx DMAx Instance 1226 * @retval State of bit (1 or 0). 1227 */ 1228 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 1229 { 1230 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); 1231 } 1232 1233 /** 1234 * @brief Get Channel 4 transfer complete flag. 1235 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 1236 * @param DMAx DMAx Instance 1237 * @retval State of bit (1 or 0). 1238 */ 1239 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 1240 { 1241 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); 1242 } 1243 1244 /** 1245 * @brief Get Channel 5 transfer complete flag. 1246 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 1247 * @param DMAx DMAx Instance 1248 * @retval State of bit (1 or 0). 1249 */ 1250 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 1251 { 1252 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); 1253 } 1254 1255 /** 1256 * @brief Get Channel 6 transfer complete flag. 1257 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 1258 * @param DMAx DMAx Instance 1259 * @retval State of bit (1 or 0). 1260 */ 1261 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 1262 { 1263 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); 1264 } 1265 1266 /** 1267 * @brief Get Channel 7 transfer complete flag. 1268 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 1269 * @param DMAx DMAx Instance 1270 * @retval State of bit (1 or 0). 1271 */ 1272 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 1273 { 1274 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); 1275 } 1276 1277 /** 1278 * @brief Get Channel 1 half transfer flag. 1279 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 1280 * @param DMAx DMAx Instance 1281 * @retval State of bit (1 or 0). 1282 */ 1283 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 1284 { 1285 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); 1286 } 1287 1288 /** 1289 * @brief Get Channel 2 half transfer flag. 1290 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 1291 * @param DMAx DMAx Instance 1292 * @retval State of bit (1 or 0). 1293 */ 1294 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 1295 { 1296 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); 1297 } 1298 1299 /** 1300 * @brief Get Channel 3 half transfer flag. 1301 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 1302 * @param DMAx DMAx Instance 1303 * @retval State of bit (1 or 0). 1304 */ 1305 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 1306 { 1307 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); 1308 } 1309 1310 /** 1311 * @brief Get Channel 4 half transfer flag. 1312 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 1313 * @param DMAx DMAx Instance 1314 * @retval State of bit (1 or 0). 1315 */ 1316 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 1317 { 1318 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); 1319 } 1320 1321 /** 1322 * @brief Get Channel 5 half transfer flag. 1323 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 1324 * @param DMAx DMAx Instance 1325 * @retval State of bit (1 or 0). 1326 */ 1327 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 1328 { 1329 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); 1330 } 1331 1332 /** 1333 * @brief Get Channel 6 half transfer flag. 1334 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 1335 * @param DMAx DMAx Instance 1336 * @retval State of bit (1 or 0). 1337 */ 1338 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 1339 { 1340 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); 1341 } 1342 1343 /** 1344 * @brief Get Channel 7 half transfer flag. 1345 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 1346 * @param DMAx DMAx Instance 1347 * @retval State of bit (1 or 0). 1348 */ 1349 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 1350 { 1351 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); 1352 } 1353 1354 /** 1355 * @brief Get Channel 1 transfer error flag. 1356 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 1357 * @param DMAx DMAx Instance 1358 * @retval State of bit (1 or 0). 1359 */ 1360 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 1361 { 1362 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); 1363 } 1364 1365 /** 1366 * @brief Get Channel 2 transfer error flag. 1367 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 1368 * @param DMAx DMAx Instance 1369 * @retval State of bit (1 or 0). 1370 */ 1371 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 1372 { 1373 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); 1374 } 1375 1376 /** 1377 * @brief Get Channel 3 transfer error flag. 1378 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 1379 * @param DMAx DMAx Instance 1380 * @retval State of bit (1 or 0). 1381 */ 1382 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 1383 { 1384 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); 1385 } 1386 1387 /** 1388 * @brief Get Channel 4 transfer error flag. 1389 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 1390 * @param DMAx DMAx Instance 1391 * @retval State of bit (1 or 0). 1392 */ 1393 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 1394 { 1395 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); 1396 } 1397 1398 /** 1399 * @brief Get Channel 5 transfer error flag. 1400 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 1401 * @param DMAx DMAx Instance 1402 * @retval State of bit (1 or 0). 1403 */ 1404 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 1405 { 1406 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); 1407 } 1408 1409 /** 1410 * @brief Get Channel 6 transfer error flag. 1411 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 1412 * @param DMAx DMAx Instance 1413 * @retval State of bit (1 or 0). 1414 */ 1415 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 1416 { 1417 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); 1418 } 1419 1420 /** 1421 * @brief Get Channel 7 transfer error flag. 1422 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 1423 * @param DMAx DMAx Instance 1424 * @retval State of bit (1 or 0). 1425 */ 1426 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 1427 { 1428 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); 1429 } 1430 1431 /** 1432 * @brief Clear Channel 1 global interrupt flag. 1433 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 1434 * @param DMAx DMAx Instance 1435 * @retval None 1436 */ 1437 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) 1438 { 1439 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); 1440 } 1441 1442 /** 1443 * @brief Clear Channel 2 global interrupt flag. 1444 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 1445 * @param DMAx DMAx Instance 1446 * @retval None 1447 */ 1448 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) 1449 { 1450 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); 1451 } 1452 1453 /** 1454 * @brief Clear Channel 3 global interrupt flag. 1455 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 1456 * @param DMAx DMAx Instance 1457 * @retval None 1458 */ 1459 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) 1460 { 1461 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); 1462 } 1463 1464 /** 1465 * @brief Clear Channel 4 global interrupt flag. 1466 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 1467 * @param DMAx DMAx Instance 1468 * @retval None 1469 */ 1470 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) 1471 { 1472 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); 1473 } 1474 1475 /** 1476 * @brief Clear Channel 5 global interrupt flag. 1477 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 1478 * @param DMAx DMAx Instance 1479 * @retval None 1480 */ 1481 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) 1482 { 1483 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); 1484 } 1485 1486 /** 1487 * @brief Clear Channel 6 global interrupt flag. 1488 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 1489 * @param DMAx DMAx Instance 1490 * @retval None 1491 */ 1492 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) 1493 { 1494 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); 1495 } 1496 1497 /** 1498 * @brief Clear Channel 7 global interrupt flag. 1499 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 1500 * @param DMAx DMAx Instance 1501 * @retval None 1502 */ 1503 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) 1504 { 1505 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); 1506 } 1507 1508 /** 1509 * @brief Clear Channel 1 transfer complete flag. 1510 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 1511 * @param DMAx DMAx Instance 1512 * @retval None 1513 */ 1514 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 1515 { 1516 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); 1517 } 1518 1519 /** 1520 * @brief Clear Channel 2 transfer complete flag. 1521 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 1522 * @param DMAx DMAx Instance 1523 * @retval None 1524 */ 1525 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 1526 { 1527 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); 1528 } 1529 1530 /** 1531 * @brief Clear Channel 3 transfer complete flag. 1532 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 1533 * @param DMAx DMAx Instance 1534 * @retval None 1535 */ 1536 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 1537 { 1538 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); 1539 } 1540 1541 /** 1542 * @brief Clear Channel 4 transfer complete flag. 1543 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 1544 * @param DMAx DMAx Instance 1545 * @retval None 1546 */ 1547 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 1548 { 1549 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); 1550 } 1551 1552 /** 1553 * @brief Clear Channel 5 transfer complete flag. 1554 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 1555 * @param DMAx DMAx Instance 1556 * @retval None 1557 */ 1558 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 1559 { 1560 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); 1561 } 1562 1563 /** 1564 * @brief Clear Channel 6 transfer complete flag. 1565 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 1566 * @param DMAx DMAx Instance 1567 * @retval None 1568 */ 1569 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 1570 { 1571 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); 1572 } 1573 1574 /** 1575 * @brief Clear Channel 7 transfer complete flag. 1576 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 1577 * @param DMAx DMAx Instance 1578 * @retval None 1579 */ 1580 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 1581 { 1582 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); 1583 } 1584 1585 /** 1586 * @brief Clear Channel 1 half transfer flag. 1587 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 1588 * @param DMAx DMAx Instance 1589 * @retval None 1590 */ 1591 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 1592 { 1593 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); 1594 } 1595 1596 /** 1597 * @brief Clear Channel 2 half transfer flag. 1598 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 1599 * @param DMAx DMAx Instance 1600 * @retval None 1601 */ 1602 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 1603 { 1604 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); 1605 } 1606 1607 /** 1608 * @brief Clear Channel 3 half transfer flag. 1609 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 1610 * @param DMAx DMAx Instance 1611 * @retval None 1612 */ 1613 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 1614 { 1615 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); 1616 } 1617 1618 /** 1619 * @brief Clear Channel 4 half transfer flag. 1620 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 1621 * @param DMAx DMAx Instance 1622 * @retval None 1623 */ 1624 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 1625 { 1626 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); 1627 } 1628 1629 /** 1630 * @brief Clear Channel 5 half transfer flag. 1631 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 1632 * @param DMAx DMAx Instance 1633 * @retval None 1634 */ 1635 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 1636 { 1637 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); 1638 } 1639 1640 /** 1641 * @brief Clear Channel 6 half transfer flag. 1642 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 1643 * @param DMAx DMAx Instance 1644 * @retval None 1645 */ 1646 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 1647 { 1648 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); 1649 } 1650 1651 /** 1652 * @brief Clear Channel 7 half transfer flag. 1653 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 1654 * @param DMAx DMAx Instance 1655 * @retval None 1656 */ 1657 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 1658 { 1659 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); 1660 } 1661 1662 /** 1663 * @brief Clear Channel 1 transfer error flag. 1664 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 1665 * @param DMAx DMAx Instance 1666 * @retval None 1667 */ 1668 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 1669 { 1670 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); 1671 } 1672 1673 /** 1674 * @brief Clear Channel 2 transfer error flag. 1675 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 1676 * @param DMAx DMAx Instance 1677 * @retval None 1678 */ 1679 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 1680 { 1681 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); 1682 } 1683 1684 /** 1685 * @brief Clear Channel 3 transfer error flag. 1686 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 1687 * @param DMAx DMAx Instance 1688 * @retval None 1689 */ 1690 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 1691 { 1692 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); 1693 } 1694 1695 /** 1696 * @brief Clear Channel 4 transfer error flag. 1697 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 1698 * @param DMAx DMAx Instance 1699 * @retval None 1700 */ 1701 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 1702 { 1703 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); 1704 } 1705 1706 /** 1707 * @brief Clear Channel 5 transfer error flag. 1708 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 1709 * @param DMAx DMAx Instance 1710 * @retval None 1711 */ 1712 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 1713 { 1714 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); 1715 } 1716 1717 /** 1718 * @brief Clear Channel 6 transfer error flag. 1719 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 1720 * @param DMAx DMAx Instance 1721 * @retval None 1722 */ 1723 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 1724 { 1725 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); 1726 } 1727 1728 /** 1729 * @brief Clear Channel 7 transfer error flag. 1730 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 1731 * @param DMAx DMAx Instance 1732 * @retval None 1733 */ 1734 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 1735 { 1736 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); 1737 } 1738 1739 /** 1740 * @} 1741 */ 1742 1743 /** @defgroup DMA_LL_EF_IT_Management IT_Management 1744 * @{ 1745 */ 1746 1747 /** 1748 * @brief Enable Transfer complete interrupt. 1749 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC 1750 * @param DMAx DMAx Instance 1751 * @param Channel This parameter can be one of the following values: 1752 * @arg @ref LL_DMA_CHANNEL_1 1753 * @arg @ref LL_DMA_CHANNEL_2 1754 * @arg @ref LL_DMA_CHANNEL_3 1755 * @arg @ref LL_DMA_CHANNEL_4 1756 * @arg @ref LL_DMA_CHANNEL_5 1757 * @arg @ref LL_DMA_CHANNEL_6 1758 * @arg @ref LL_DMA_CHANNEL_7 1759 * @retval None 1760 */ 1761 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 1762 { 1763 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); 1764 } 1765 1766 /** 1767 * @brief Enable Half transfer interrupt. 1768 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT 1769 * @param DMAx DMAx Instance 1770 * @param Channel This parameter can be one of the following values: 1771 * @arg @ref LL_DMA_CHANNEL_1 1772 * @arg @ref LL_DMA_CHANNEL_2 1773 * @arg @ref LL_DMA_CHANNEL_3 1774 * @arg @ref LL_DMA_CHANNEL_4 1775 * @arg @ref LL_DMA_CHANNEL_5 1776 * @arg @ref LL_DMA_CHANNEL_6 1777 * @arg @ref LL_DMA_CHANNEL_7 1778 * @retval None 1779 */ 1780 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 1781 { 1782 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); 1783 } 1784 1785 /** 1786 * @brief Enable Transfer error interrupt. 1787 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE 1788 * @param DMAx DMAx Instance 1789 * @param Channel This parameter can be one of the following values: 1790 * @arg @ref LL_DMA_CHANNEL_1 1791 * @arg @ref LL_DMA_CHANNEL_2 1792 * @arg @ref LL_DMA_CHANNEL_3 1793 * @arg @ref LL_DMA_CHANNEL_4 1794 * @arg @ref LL_DMA_CHANNEL_5 1795 * @arg @ref LL_DMA_CHANNEL_6 1796 * @arg @ref LL_DMA_CHANNEL_7 1797 * @retval None 1798 */ 1799 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 1800 { 1801 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); 1802 } 1803 1804 /** 1805 * @brief Disable Transfer complete interrupt. 1806 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC 1807 * @param DMAx DMAx Instance 1808 * @param Channel This parameter can be one of the following values: 1809 * @arg @ref LL_DMA_CHANNEL_1 1810 * @arg @ref LL_DMA_CHANNEL_2 1811 * @arg @ref LL_DMA_CHANNEL_3 1812 * @arg @ref LL_DMA_CHANNEL_4 1813 * @arg @ref LL_DMA_CHANNEL_5 1814 * @arg @ref LL_DMA_CHANNEL_6 1815 * @arg @ref LL_DMA_CHANNEL_7 1816 * @retval None 1817 */ 1818 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 1819 { 1820 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); 1821 } 1822 1823 /** 1824 * @brief Disable Half transfer interrupt. 1825 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT 1826 * @param DMAx DMAx Instance 1827 * @param Channel This parameter can be one of the following values: 1828 * @arg @ref LL_DMA_CHANNEL_1 1829 * @arg @ref LL_DMA_CHANNEL_2 1830 * @arg @ref LL_DMA_CHANNEL_3 1831 * @arg @ref LL_DMA_CHANNEL_4 1832 * @arg @ref LL_DMA_CHANNEL_5 1833 * @arg @ref LL_DMA_CHANNEL_6 1834 * @arg @ref LL_DMA_CHANNEL_7 1835 * @retval None 1836 */ 1837 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 1838 { 1839 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); 1840 } 1841 1842 /** 1843 * @brief Disable Transfer error interrupt. 1844 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE 1845 * @param DMAx DMAx Instance 1846 * @param Channel This parameter can be one of the following values: 1847 * @arg @ref LL_DMA_CHANNEL_1 1848 * @arg @ref LL_DMA_CHANNEL_2 1849 * @arg @ref LL_DMA_CHANNEL_3 1850 * @arg @ref LL_DMA_CHANNEL_4 1851 * @arg @ref LL_DMA_CHANNEL_5 1852 * @arg @ref LL_DMA_CHANNEL_6 1853 * @arg @ref LL_DMA_CHANNEL_7 1854 * @retval None 1855 */ 1856 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 1857 { 1858 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); 1859 } 1860 1861 /** 1862 * @brief Check if Transfer complete Interrupt is enabled. 1863 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC 1864 * @param DMAx DMAx Instance 1865 * @param Channel This parameter can be one of the following values: 1866 * @arg @ref LL_DMA_CHANNEL_1 1867 * @arg @ref LL_DMA_CHANNEL_2 1868 * @arg @ref LL_DMA_CHANNEL_3 1869 * @arg @ref LL_DMA_CHANNEL_4 1870 * @arg @ref LL_DMA_CHANNEL_5 1871 * @arg @ref LL_DMA_CHANNEL_6 1872 * @arg @ref LL_DMA_CHANNEL_7 1873 * @retval State of bit (1 or 0). 1874 */ 1875 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 1876 { 1877 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 1878 DMA_CCR_TCIE) == (DMA_CCR_TCIE)); 1879 } 1880 1881 /** 1882 * @brief Check if Half transfer Interrupt is enabled. 1883 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT 1884 * @param DMAx DMAx Instance 1885 * @param Channel This parameter can be one of the following values: 1886 * @arg @ref LL_DMA_CHANNEL_1 1887 * @arg @ref LL_DMA_CHANNEL_2 1888 * @arg @ref LL_DMA_CHANNEL_3 1889 * @arg @ref LL_DMA_CHANNEL_4 1890 * @arg @ref LL_DMA_CHANNEL_5 1891 * @arg @ref LL_DMA_CHANNEL_6 1892 * @arg @ref LL_DMA_CHANNEL_7 1893 * @retval State of bit (1 or 0). 1894 */ 1895 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 1896 { 1897 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 1898 DMA_CCR_HTIE) == (DMA_CCR_HTIE)); 1899 } 1900 1901 /** 1902 * @brief Check if Transfer error Interrupt is enabled. 1903 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE 1904 * @param DMAx DMAx Instance 1905 * @param Channel This parameter can be one of the following values: 1906 * @arg @ref LL_DMA_CHANNEL_1 1907 * @arg @ref LL_DMA_CHANNEL_2 1908 * @arg @ref LL_DMA_CHANNEL_3 1909 * @arg @ref LL_DMA_CHANNEL_4 1910 * @arg @ref LL_DMA_CHANNEL_5 1911 * @arg @ref LL_DMA_CHANNEL_6 1912 * @arg @ref LL_DMA_CHANNEL_7 1913 * @retval State of bit (1 or 0). 1914 */ 1915 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 1916 { 1917 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 1918 DMA_CCR_TEIE) == (DMA_CCR_TEIE)); 1919 } 1920 1921 /** 1922 * @} 1923 */ 1924 1925 #if defined(USE_FULL_LL_DRIVER) 1926 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions 1927 * @{ 1928 */ 1929 1930 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); 1931 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); 1932 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); 1933 1934 /** 1935 * @} 1936 */ 1937 #endif /* USE_FULL_LL_DRIVER */ 1938 1939 /** 1940 * @} 1941 */ 1942 1943 /** 1944 * @} 1945 */ 1946 1947 #endif /* DMA1 || DMA2 */ 1948 1949 /** 1950 * @} 1951 */ 1952 1953 #ifdef __cplusplus 1954 } 1955 #endif 1956 1957 #endif /* __STM32F1xx_LL_DMA_H */ 1958