1 /* 2 * Copyright (c) 2023 Juan Manuel Cruz <jcruz@fi.uba.ar> <jcruz@frba.utn.edu.ar>. 3 * 4 * See file `LICENSE` for full details 5 */ 6 7 #ifndef BOARD_INC_BOARD_H_ 8 #define BOARD_INC_BOARD_H_ 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 #define NUCLEO_F103RC (0) 15 #define NUCLEO_F303R8 (1) 16 #define NUCLEO_F401RE (2) 17 #define NUCLEO_F446RE (3) 18 #define NUCLEO_F413ZH (4) 19 #define NUCLEO_F429ZI (5) 20 #define NUCLEO_F439ZI (6) 21 #define NUCLEO_F767ZI (7) 22 #define STM32F407G_DISC1 (8) 23 #define STM32F429I_DISC1 (9) 24 25 #define BOARD (NUCLEO_F103RC) 26 27 /* STM32 Nucleo Boards - 32 Pins */ 28 #if (BOARD == NUCLEO_F303R8) 29 30 #endif 31 32 /* STM32 Nucleo Boards - 64 Pins */ 33 #if ((BOARD == NUCLEO_F103RC) || (BOARD == NUCLEO_F401RE) || (BOARD == NUCLEO_F446RE)) 34 35 #define BTN_A_PIN B1_Pin 36 #define BTN_A_PORT B1_GPIO_Port 37 #define BTN_A_PRESSED GPIO_PIN_RESET 38 #define BTN_A_HOVER GPIO_PIN_SET 39 40 #define LED_A_PIN LD2_Pin 41 #define LED_A_PORT LD2_GPIO_Port 42 #define LED_A_ON GPIO_PIN_SET 43 #define LED_A_OFF GPIO_PIN_RESET 44 45 #endif 46 47 /* STM32 Nucleo Boards - 144 Pins */ 48 #if ((BOARD == NUCLEO_F413ZH) || (BOARD == NUCLEO_F429ZI) || (BOARD == NUCLEO_F439ZI) || (BOARD == NUCLEO_F767ZI)) 49 50 #define BTN_A_PIN USER_Btn_Pin 51 #define BTN_A_PORT USER_Btn_GPIO_Port 52 #define BTN_A_PRESSED GPIO_PIN_SET 53 #define BTN_A_HOVER GPIO_PIN_RESET 54 55 #define LED_A_PIN LD1_Pin 56 #define LED_A_PORT LD1_GPIO_Port 57 #define LED_A_ON GPIO_PIN_SET 58 #define LED_A_OFF GPIO_PIN_RESET 59 60 #endif 61 62 /* STM32 Discovery Kits */ 63 #if ((BOARD == STM32F407G_DISC1) || (BOARD == STM32F429I_DISC1)) 64 65 #define BTN_A_PIN B1_Pin 66 #define BTN_A_PORT B1_GPIO_Port 67 #define BTN_A_PRESSED GPIO_PIN_SET 68 #define BTN_A_HOVER GPIO_PIN_RESET 69 70 #define LED_A_PIN LD3_Pin 71 #define LED_A_PORT LD3_GPIO_Port 72 #define LED_A_ON GPIO_PIN_SET 73 #define LED_A_OFF GPIO_PIN_RESET 74 75 #endif 76 77 #ifdef __cplusplus 78 } 79 #endif 80 81 #endif /* BOARD_INC_BOARD_H_ */
