TB066

Análisis de Circuitos (TB066)
Index Commits Files Refs
tp/board/board.kicad_prl (2520B)
   1 {
   2   "board": {
   3     "active_layer": 2,
   4     "active_layer_preset": "",
   5     "auto_track_width": true,
   6     "hidden_netclasses": [],
   7     "hidden_nets": [],
   8     "high_contrast_mode": 0,
   9     "net_color_mode": 1,
  10     "opacity": {
  11       "images": 0.6,
  12       "pads": 1.0,
  13       "shapes": 1.0,
  14       "tracks": 1.0,
  15       "vias": 1.0,
  16       "zones": 0.6
  17     },
  18     "prototype_zone_fills": false,
  19     "selection_filter": {
  20       "dimensions": true,
  21       "footprints": true,
  22       "graphics": true,
  23       "keepouts": true,
  24       "lockedItems": false,
  25       "otherItems": true,
  26       "pads": true,
  27       "text": true,
  28       "tracks": true,
  29       "vias": true,
  30       "zones": true
  31     },
  32     "visible_items": [
  33       "vias",
  34       "footprint_text",
  35       "footprint_anchors",
  36       "ratsnest",
  37       "grid",
  38       "footprints_front",
  39       "footprints_back",
  40       "footprint_values",
  41       "footprint_references",
  42       "tracks",
  43       "drc_errors",
  44       "drawing_sheet",
  45       "bitmaps",
  46       "pads",
  47       "zones",
  48       "drc_warnings",
  49       "drc_exclusions",
  50       "locked_item_shadows",
  51       "conflict_shadows",
  52       "shapes",
  53       "board_outline_area",
  54       "ly_points"
  55     ],
  56     "visible_layers": "ffffffff_ffffffff_fffffff7_ffffffff",
  57     "zone_display_mode": 0
  58   },
  59   "git": {
  60     "integration_disabled": false,
  61     "repo_type": "",
  62     "repo_username": "",
  63     "ssh_key": ""
  64   },
  65   "meta": {
  66     "filename": "board.kicad_prl",
  67     "version": 5
  68   },
  69   "net_inspector_panel": {
  70     "col_hidden": [
  71       false,
  72       false,
  73       false,
  74       false,
  75       false,
  76       false,
  77       false,
  78       false,
  79       false,
  80       false
  81     ],
  82     "col_order": [
  83       0,
  84       1,
  85       2,
  86       3,
  87       4,
  88       5,
  89       6,
  90       7,
  91       8,
  92       9
  93     ],
  94     "col_widths": [],
  95     "custom_group_rules": [],
  96     "expanded_rows": [],
  97     "filter_by_net_name": true,
  98     "filter_by_netclass": true,
  99     "filter_text": "",
 100     "group_by_constraint": false,
 101     "group_by_netclass": false,
 102     "show_time_domain_details": false,
 103     "show_unconnected_nets": false,
 104     "show_zero_pad_nets": false,
 105     "sort_ascending": true,
 106     "sorting_column": -1
 107   },
 108   "open_jobsets": [],
 109   "project": {
 110     "files": []
 111   },
 112   "schematic": {
 113     "hierarchy_collapsed": [],
 114     "selection_filter": {
 115       "graphics": true,
 116       "images": true,
 117       "labels": true,
 118       "lockedItems": false,
 119       "otherItems": true,
 120       "pins": true,
 121       "ruleAreas": true,
 122       "symbols": true,
 123       "text": true,
 124       "wires": true
 125     }
 126   }
 127 }