# VHDL Examples

> NOTE: All vhdl containing keyword `wait` is not synthesizable, its only
> purpose is to test the device. In that case the best practice is to separate
> the module containing the device itself from the module containing the test
> case. Thats why in the `dev` folder modules are located on the non `_tb`
> ending file, and the test case, containing the non synthesizable parts are
> located on files ending with `_tb`.

## Resources used

[Basic VHDL course](https://www.youtube.com/playlist?list=PLIbRYKjjYOPkhpxnkQ0fwTXnmgsiCMcVV)