reg_tb.vhd - TA147 - Ejecicios y trabajos prácticos de la materia Taller de Sistemas Digitales (TA147)

vhdl/dev/reg/reg_tb.vhd (764B)

Line numbers

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 
   5 entity reg_tb is
   6 end entity;
   7 
   8 architecture reg_arq of reg_tb is
   9 
  10     constant N : integer := 4;
  11 
  12     signal sig_D   : std_logic_vector(N-1 downto 0) := (others => '0');
  13     signal sig_Q   : std_logic_vector(N-1 downto 0);
  14     signal sig_clk : std_logic := '0';
  15     signal sig_rst : std_logic := '0';
  16     signal sig_ena : std_logic := '1';
  17 
  18 begin
  19 
  20     flip_flop_d : entity work.reg(reg_arq)
  21     generic map(N => N)
  22     port map(
  23         D   => sig_D,
  24         Q   => sig_Q,
  25         clk => sig_clk,
  26         rst => sig_rst,
  27         ena => sig_ena);
  28 
  29     sig_D <= (others => '1') after 5 us;
  30     sig_clk <= not sig_clk after 1 us;
  31     sig_rst <= '1' after 10 us, '0' after 20 us;
  32 
  33 end architecture;