vhdl/dev/button_controlled_led/button_controlled_led_tb.vhd (557B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity button_controlled_led_tb is 6 end entity; 7 8 architecture button_controlled_led_arq of button_controlled_led_tb is 9 10 signal sig_button : std_logic := '0'; 11 signal sig_led : std_logic; 12 13 begin 14 15 DUT : entity work.button_controlled_led(button_controlled_led_arq) port map( 16 button_a => sig_button, 17 led_a => sig_led); 18 19 process is 20 begin 21 22 sig_button <= not sig_button after 250 us; 23 wait for 10 us; 24 25 end process; 26 27 end architecture;