vhdl/dev/adder_generic/reg.vhd (662B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity reg is 6 generic(N: integer:= 4); 7 port( 8 -- inputs 9 D : in std_logic_vector(N-1 downto 0); 10 clk : in std_logic; 11 rst : in std_logic; 12 ena : in std_logic; 13 14 -- outputs 15 Q : out std_logic_vector(N-1 downto 0) 16 ); 17 end; 18 19 architecture reg_arq of reg is 20 begin 21 22 process(clk, rst) 23 begin 24 25 if rising_edge(clk) then 26 if rst = '1' then 27 Q <= (others => '0'); 28 elsif ena = '1' then 29 Q <= D; 30 end if; 31 end if; 32 33 end process; 34 35 end architecture;