tps/1/src/rtl/semaphore.vhd (2308B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use work.semaphore_pkg.all; 4 5 entity semaphore is 6 7 generic(clk_freq : integer := 1e6); -- default 1 MHz clock frequency 8 port( 9 clk : in std_logic; 10 rst : in std_logic; 11 state_flag : in std_logic; 12 13 red_1 : out std_logic; 14 yel_1 : out std_logic; 15 gre_1 : out std_logic; 16 red_2 : out std_logic; 17 yel_2 : out std_logic; 18 gre_2 : out std_logic; 19 state : out state_t); 20 21 end entity; 22 23 architecture semaphore_arq of semaphore is 24 25 -- R1 Y1 G1 R2 Y2 G2 26 signal light : std_logic_vector(5 downto 0); 27 28 signal state_aux : state_t; 29 30 begin 31 32 process(rst, clk) is 33 begin 34 35 if rst = '1' then 36 state_aux <= state_1r_2g; 37 elsif rising_edge(clk) then 38 39 case state_aux is 40 when state_1r_2g => 41 if state_flag = '1' then 42 state_aux <= state_1r_2y; 43 end if; 44 when state_1r_2y => 45 if state_flag = '1' then 46 state_aux <= state_1ry_2r; 47 end if; 48 when state_1ry_2r => 49 if state_flag = '1' then 50 state_aux <= state_1g_2r; 51 end if; 52 when state_1g_2r => 53 if state_flag = '1' then 54 state_aux <= state_1y_2r; 55 end if; 56 when state_1y_2r => 57 if state_flag = '1' then 58 state_aux <= state_1r_2ry; 59 end if; 60 when state_1r_2ry=> 61 if state_flag = '1' then 62 state_aux <= state_1r_2g; 63 end if; 64 end case; 65 66 end if; 67 68 end process; 69 70 state <= state_aux; 71 72 -- R1 Y1 G1 R2 Y2 G2 73 with state_aux select light <= 74 "100001" when state_1r_2g, 75 "100010" when state_1r_2y, 76 "010100" when state_1ry_2r, 77 "001100" when state_1g_2r, 78 "010100" when state_1y_2r, 79 "100010" when state_1r_2ry; 80 81 red_1 <= light(5); 82 yel_1 <= light(4); 83 gre_1 <= light(3); 84 red_2 <= light(2); 85 yel_2 <= light(1); 86 gre_2 <= light(0); 87 88 end architecture;