tps/1/src/rtl/cnt.vhd (1654B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 use work.semaphore_pkg.all; 6 7 entity cnt is 8 port( 9 clk : in std_logic; 10 rst : in std_logic; 11 ena : in std_logic; 12 state : in state_t; 13 14 state_flag : out std_logic); 15 end; 16 17 architecture cnt_arq of cnt is 18 19 constant YELLOW_S : unsigned(5 downto 0) := to_unsigned(3, 6); 20 constant RED_GREEN_S : unsigned(5 downto 0) := to_unsigned(30, 6); 21 22 signal tick_cnt : unsigned(5 downto 0); 23 24 begin 25 26 process(clk, rst) 27 begin 28 29 if rst = '1' then 30 31 tick_cnt <= (others => '0'); 32 33 elsif rising_edge(clk) then 34 35 if ena = '1' then 36 if state /= state_1r_2g and state /= state_1g_2r then 37 if tick_cnt = YELLOW_S - 1 then 38 tick_cnt <= (others => '0'); 39 40 else 41 tick_cnt <= tick_cnt + 1; 42 end if; 43 44 else 45 if tick_cnt = RED_GREEN_S - 1 then 46 tick_cnt <= (others => '0'); 47 else 48 tick_cnt <= tick_cnt + 1; 49 end if; 50 end if; 51 52 end if; 53 54 end if; 55 56 end process; 57 58 state_flag <= 59 '1' when rst = '0' and 60 ena = '1' and 61 state /= state_1r_2g and 62 state /= state_1g_2r and 63 tick_cnt = YELLOW_S - 1 64 else 65 '1' when rst = '0' and 66 ena = '1' and 67 tick_cnt = RED_GREEN_S - 1 68 else 69 '0'; 70 71 end architecture;